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| RF9936 8 Typical Applications * CDMA/TDMA/DCS1900 PCS Systems * PHS 1500/WLAN 2400 Systems * Receivers Employing Diversity Antennas * General Purpose Downconverter * Micro-Cell PCS Base Stations * Portable Battery Powered Equipment PCS LOW NOISE AMPLIFIER/MIXER D R ES F9 98 IG 6N S .157 .150 .033 1 Product Description N E ro W d .050 .016 .010 .008 Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS ! Package Style: SSOP-24 GaAs HBT SiGe HBT GaAs MESFET Si CMOS Features * Complete Receiver Front-End * Analog RF Gain Control * Single 3.6V Power Supply * Digitally Selectable LNA Inputs * Digitally Selectable Buffered LO Output * 1500MHz to 2500MHz Operation LNA SEL 1 VCC1 2 VCC2 3 N SO ee T LNA2 IN 5 GND2 6 GND3 7 LNA1 IN 8 GND4 9 UF pg O ra R de d P 24 GC GAIN ADJUST 23 GND9 22 VCC4 GND1 4 21 GND8 20 LNA OUT 19 GND7 SEL. LOGIC 18 MIX RF IN 17 GND6 16 IF15 IF+ 14 GND5 VCC3 10 Ordering Information RF9936 RF9936 PCBA PCS Low Noise Amplifier/Mixer Fully Assembled Evaluation Board LO BUFF EN 11 LO IN 12 13 LO BUFF OUT Functional Block Diagram RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A8 000822 8-121 FRONT-ENDS uc t The RF9936 is a monolithic integrated receiver front-end for PCS applications. The IC contains all of the required components to implement the RF functions of the receiver front-end except for the passive filtering and LO generation. It contains two LNAs (low-noise amplifiers), a double-balanced Gilbert cell mixer, a balanced IF output, an LO isolation buffer amplifier, and an LO output buffer amplifier for providing the buffered LO signal as an output. On-chip digital logic is used to enable the appropriate LNA. The LNAs share a common output that permits insertion of a bandpass filter between the LNA output and the Mixer section. Analog gain adjustment is provided which allows 10dB variation in gain. The IC is designed to operate from a single 3.6V power supply. .010 .004 .344 .337 .012 .008 .025 .244 .228 .069 .053 8MAX 0MIN 8 RF9936 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Ambient Operating Temperature Storage Temperature Rating -0.5 to 7.0 +6 -40 to +85 -40 to +150 Unit VDC dBm C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall RF Frequency Range LO Frequency Range IF Frequency Range Specification Min. Typ. Max. 1500 to 2500 1200 to 2500 DC to 500 Unit Condition T = 25C, VCC =3.6V, RF=1959MHz, LO=1749MHz @ -2dBm Cascaded Performance Cascade Conversion Gain, Maximum Cascade Conversion Gain, Minimum Cascade Input IP3 Cascade Noise Figure FRONT-ENDS 27.5 15.5 -14 -9 2.5 5.1 8 First Section (LNA) Noise Figure Input VSWR Input IP3 N E ro W d 1.4 <2.5:1 +2 13.5 23 <1.5:1 6.5 13.5 1.5:1 -3 +2 16 6 1 uc t dB dBm dB dB dB dB dBm dBm dB dB k N SO ee T Gain Reverse Isolation Output VSWR UF pg O ra R de d P Second Section (Mixer) Noise Figure Input VSWR Input IP3 Conversion Gain, Maximum Conversion Gain, Minimum Output Impedance 8-122 D R ES F9 98 IG 6N S MHz MHz MHz dB dB VG 2.5V dBm dBm dB dB At maximum gain At minimum gain VG 0.2V VG 2.5V Balanced 1k balanced load, 2.5dB Image Filter Loss. By varying the gain of the second stage, a trade-off of gain and noise figure against IP3 can be made. VG 0.5V Maximum Gain Minimum Gain Single sideband, at Maximum Gain Setting Single sideband, at Minimum Gain Setting The LNA section may be left unused. Power is not connected to pin 1. The performance is then as specified for the Second Section (Mixer). Input is internally matched for optimum noise figure from a 50 source. IP3 may be increased 10dB by connecting pin 22 to VCC through the matching inductor. The LNA's current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made. See pin description for pin 20. With 1k balanced load. By varying the gain of the second stage, a trade-off of gain and noise figure against IP3 can be made. Please see data plots. Single Sideband, at maximum gain Single Sideband, at minimum gain Rev A8 000822 RF9936 Parameter LO Input LO Input Range LO Output Level LO to RF (Mix In) Rejection LO to IF1, IF2 Rejection LO Input VSWR -5 to +3 -5 -25 30 20 <2:1 3.65% 5 46 43 dBm dBm dBm dB dB Buffer On, -2dBm input Buffer Off, -2dBm input Specification Min. Typ. Max. Unit Condition Single ended V mA mA mA Power Supply Voltage Current Consumption D R ES F9 98 IG 6N S 50 47 LNA only LNA + Mixer, LO Buffer On LNA + Mixer, LO Buffer Off 8 FRONT-ENDS N SO ee T Rev A8 000822 UF pg O ra R de d P N E ro W d uc t 8-123 RF9936 Pin 1 Function LNA SEL Description Selects which LNA (LNA1 or LNA2) is active. This is a digitally controlled input. A logic "high" (3.1V.) selects LNA2. A logic "low" (0.5V.) selects LNA1. Supply Voltage for the Mixer and RF Buffer Amplifier. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Supply Voltage for the LNAs and associated select logic. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Ground connection for LNA2. Keep traces physically short and connect immediately to ground plane for best performance. RF Input pin for LNA2. This pin is internally DC blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50 source impedance. Same as pin 4. Ground connection for LNA1. Keep traces physically short and connect immediately to ground plane for best performance. RF Input pin for LNA1. This pin is internally DC blocked and internally matched for minimum noise figure (NOT for minimum VSWR), given a 50 source impedance. Same as pin 7. Supply voltage for both LO buffer amplifiers. External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Enable pin for the LO output buffer amplifier. This is a digitally controlled input. A logic "high" (3.1V.) turns the buffer amplifier on, and the current consumption increases by 3mA (with -2dBm LO input). A logic "low" (0.5V.) turns the buffer amplifier off. Interface Schematic LNA SEL 10 k 2 VCC1 150 VCC1 BIAS VCC4 3 VCC2 4 5 6 7 8 9 10 GND1 LNA2 IN GND2 GND3 LNA1 IN GND4 VCC3 8 FRONT-ENDS 11 LO BUFF EN LO IN LO BUFF OUT GND5 IF+ N E ro W d uc t D R ES F9 98 IG 6N S LO BUFF EN 7.5 k IF1 k IF+ 12 13 14 15 N SO ee T 16 17 18 IFGND6 Mixer LO Input pin. This pin is internally DC blocked and matched to 50. Optional Buffered LO Output. This pin is internally DC blocked and matched to 50. The buffer amplifier is switched on or off by the voltage level at pin 11. Ground connection for both LO buffer amplifiers. Keep traces physically short and connect immediately to ground plane for best performance. Open-collector IF Output pin. This is a balanced output. The output impedance is set by an internal 1000 resistor to pin 16. Thus the differential IF output impedance is 1000. The resistor sets the operating impedance, but an external choke or matching inductor to VCC must be supplied in order to bias this output. This inductor is typically incorporated in the matching network between the output and IF filter. Because this pin is biased to VCC, a DC blocking capacitor must be used if the IF filter input has a DC path to ground. Same as pin 15, except complementary output. Ground connection for the Mixer. Keep traces physically short and connect immediately to ground plane for best performance. Mixer RF Input Pin. This pin is internally DC blocked and matched to 50. Same as pin 17. UF pg O ra R de d P See pin 15. MIX RF IN GND7 19 8-124 Rev A8 000822 RF9936 Pin 20 Function LNA OUT Description LNA Output pin. This is an open-collector output. This pin is typically connected to pin 22 through a bias/matching inductor. This inductor, in conjunction with a series blocking/matching capacitor, forms a matching network to the 50 image filter and provides bias (see Application Example). The LNA's IP3 may be increased 10dB by connecting pin 20 to VCC through the inductor. The LNA's current then increases by 10mA. Other in-between IP3 vs. ICC trade-offs may be made by connecting resistance values between VCC and the matching inductor. The two reference points for consideration are with 150 used, which is what connection to pin 22 achieves, the Input IP3 is +2dBm and the LNA ICC is 5mA. Using no resistance, the Input IP3 is +12 dBm and the LNA ICC is 15 mA. Desired operating points in between these values may be interpolated, roughly. Same as pin 17. Interface Schematic LNA OUT 21 22 GND8 VCC4 23 24 GND9 GC Output supply voltage for the LNA Output (pin 20). This pin should NOT be connected to a voltage supply. This pin should be connected to pin 20 through a bias/matching inductor (see Application Example). External RF bypassing is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. Same as pin 17. Analog gain adjustment for RF buffer amplifier. Minimum gain is selected with 2.5V to 3.0V. Maximum gain is selected with 0V to 0.5 V. When operating the RF9936 at fixed maximum gain, this pin may be grounded. D R ES F9 98 IG 6N S GC See pin 2. 150 350 8 FRONT-ENDS N SO ee T Rev A8 000822 UF pg O ra R de d P N E ro W d uc t 8-125 RF9936 Application Schematic LNA SEL VCC 1 2 3 68 pF 4 24 23 68 pF 22 21 20 2.7 nH GC (Min Gain: 3.1V, Max Gain: 0.5V) GAIN ADJUST RF2 IN 5 6 7 SEL. LOGIC RF1 IN 8 9 D R ES F9 98 IG 6N S 19 18 17 16 15 14 13 RF Image Filter, 50 1 nF VCC ZFILTER = 1 k 68 pF C1 L1 C2 C2 Filter 68 pF C1 L1 VCC 1 nF ZOUT = 1 k 1.8 pF IFIF+ VCC 68 pF 10 LO BUFF EN (On: 3.1v, Off: 0.5V) LO IN 11 12 Measurement Reference Plane LO BUFF OUT 8 FRONT-ENDS N SO ee T 8-126 UF pg O ra R de d P N E ro W d L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network if the IF filter's input impedance is not 100 . Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit at the IF when the IF filter's input impedance is 100 . uc t Rev A8 000822 RF9936 Evaluation Board Schematic IF 210MHz (Download Bill of Materials from www.rfmd.com.) R1 1 k P2-1 C15 1 nF 1 2 P1-1 3 4 LNA2 IN J2 50 strip 5 6 LNA1 IN J1 50 strip 7 8 9 10 11 50 strip J3 12 24 23 22 21 20 19 18 17 16 15 14 13 L1 2.7 nH 1 3 C1 22 pF see notes 6 FL1 (SAW Filter) 4 C14 1 nF C10 22 pF P2-3 C2 22 pF see notes Drawing 9936401 Rev A P1 GAIN ADJUST 50 strip LNA OUT J7 P1-1 1 2 VCC GND BUFFER ENABLE C17 1 nF C16 22 pF P1-3 3 P2 2 D R ES F9 98 IG 6N S C4 3.9 pF C5 22 pF see notes 5 50 strip MIXER IN J6 L6 39 nH L7 39 nH C21 1 pF C6 100 pF C7 100 pF C3 22 pF see notes C8 5.1 pF C22 1 pF L5 180 nH T1 5.5:1 C11 1.5 pF L4 47 nH L2 470 nH C13 22 pF L3 470 nH C9 1 nF C12 1 nF C24 4.7 F P2-1 1 2 LNA SELECT GND GC SEL. LOGIC P2-3 3 P1-1 C19 1 nF C18 22 pF IF OUT 50 strip J4 R2 1 k P1-3 LO IN C23 1 nF C20 22 pF N E ro W d N SO ee T Rev A8 000822 UF pg O ra R de d P 8-127 FRONT-ENDS uc t Note: 1) For cascaded LNA/MIXER applications, install C1 and C5 and remove C2 and C3 (default configuration). 2) For LNA only and/or MIXER only characterization, install C2 and remove C1 and C5. 3) L5 select value 180 nH to 220 nH. 4) Do not install C2, C3 in normal cascade operation. 50 strip LO OUT J5 8 RF9936 Evaluation Board Layout (Assembly, Top layer, Mid-signal layer, Internal Ground layer) 8 FRONT-ENDS N SO ee T 8-128 UF pg O ra R de d P N E ro W d uc t D R ES F9 98 IG 6N S Rev A8 000822 Rev A8 000822 N SO ee T UF pg O ra R de d P Evaluation Board Layout cont'd N E ro W d uc t D R ES F9 98 IG 6N S RF9936 8-129 8 FRONT-ENDS 8 FRONT-ENDS 8-130 RF9936 N SO ee T UF pg O ra R de d P N E ro W d uc t D R ES F9 98 IG 6N S Rev A8 000822 |
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